1. Field of the Invention
The present invention relates to a liquid crystal display device and, more particularly, to an art useful in application to video signal line driving means of a liquid crystal display device capable of providing multilevel grayscale display.
2. Description of the Related Art
Liquid crystal display devices are widely used as display devices for OA equipment such as personal computers. The liquid crystal display devices are mainly classified into a simple matrix type in which pixels are formed at the intersections of stripe-shaped electrodes disposed to intersect with one another, and an active matrix type which has an active element such as a thin-film transistor (TFT) for each pixel and turns on and off the active element.
The active matrix type of liquid crystal display device includes a TFT liquid crystal panel, scanning signal line driving means and video signal line driving means for supplying a scanning voltage and a video signal voltage, respectively, to scanning signal lines (gate lines) and video signal lines (drain lines) all of which are disposed over this liquid crystal panel, and a display control unit as well as an internal power supply circuit for supplying various control signals and display data outputted from a host side such as a personal computer, to the scanning signal line driving means and the video signal line driving means as displaying signals.
FIG. 28 is a schematic block diagram illustrating the construction of a liquid crystal display device to which the present invention is applied. A liquid crystal panel 281 which constitutes this liquid crystal display device is a thin-film transistor type of active matrix liquid crystal display device (TFT-LCD), and a plurality of video signal line driving circuits (hereinafter referred to also as drain drivers) 282 and a plurality of scanning signal line driving circuits (hereinafter referred to also as gate drivers) 283 are arranged over the top side of the liquid crystal panel 281.
The liquid crystal panel 281 is made of, for example, 1024xc3x97768 picture elements (pixels: Pix) each of which is formed by three color pixels of red (R), green (G) and blue (B).
A control signal, which is made of three color display data (video signals) for red (R), green (G) and blue (B), a clock signal, a display timing signal and a synchronizing signal all of which are outputted from the host side such as a personal computer, is inputted to a display control device 285 via an interface connector 284.
The display control device 285 generates display data of a form displayable on the liquid crystal panel on the basis of the control signal, and supplies the display data to the drain drivers 282 via a data bus. At the same time, the display control device 285 supplies timing signals, (a carry input, CLK1, CLK2) such as a display start timing clock, a line clock and a pixel clock to the drain drivers 282.
An internal power supply circuit 286 generates a reference voltage (V9 to V0) for producing a display grayscale and supplies the reference voltage to the drain drivers 282, and also applies a scanning voltage (a gate voltage) to the gate drivers 283.
Each of the drain drivers 282 is assigned to a predetermined number of video signal lines (drain lines), and is arranged to serially give a carry output to the next drain driver after a predetermined number of counts.
Each of the drain drivers 282 is provided with a grayscale generation circuit for generating a grayscale voltage corresponding to display data for the drain lines and an amplifying circuit for amplifying the generated grayscale voltage and outputting a video signal voltage corresponding to the display data to each of the drain lines.
In addition, in the TFT type of liquid crystal display device, to prevent burn-in on a liquid crystal layer, the grayscale voltage to be applied to the drain lines needs to be inverted in polarity with respect to a counter electrode (hereinafter, VCOM) for each frame. As methods of realizing this, there are VCOM alternating current driving which varies the polarity of the counter electrode as well, and dot inversion driving which varies the drain lines to a great extent with the counter electrode being retained in a fixed potential.
This kind of driving of a liquid crystal display device is disclosed in, for example, Japanese Patent Laid-Open No. 281930/1997.
In recent years, the trend in TFT types of active matrix liquid crystal display devices has been toward larger screen sizes in liquid crystal panels (TFT-LCD), higher resolution, higher image quality and lower power consumption. In addition, in order to omit a useless space and improve the appearance of a display device, it has been demanded that the size of its frame portion be made as small as possible.
In other words, as the market becomes more mature, it is becoming more indispensable to lower the prices of liquid crystal display devices, and further reductions in the mounting areas of drain drivers as well as reductions in the sizes of frame portions are demanded. In addition, as notebook personal computers become more widely used, the necessity for long-time driving using batteries increases and lower power consumption in liquid crystal display devices is demanded.
As described above, a grayscale voltage to be applied to a drain line needs to be inverted in polarity with respect to the voltage VCOM of a counter electrode for each frame. However, while the gate voltage of a TFT is changing from its on state to its off state, the gate-fo-source capacitance (Cgs) of the TFT assumes a depletion state, so that the voltage applied to the liquid crystal, i.e., the output voltage of a drain driver penetrates into this depletion portion.
Therefore, for example if the TFT is of an n type, the voltage at the gate electrode is lower during the off state than during the on state, so that since a positive voltage penetrates into a drain side, an effective voltage to be applied to the liquid crystal is lower than the output of the drain driver. Accordingly, in view of this penetration, in the n-type of TFT, it is necessary that during the application of a negative side (a low voltage side) relative to VCOM, the output voltage of the drain driver be made higher than the voltage required in the absence of the penetration.
For the above-described reason, to equalize the effective voltages of negative and positive sides relative to VCOM, it is necessary to adopt asymmetric driving in which the output voltage of the drain driver is asymmetric with respect to VCOM between the negative side (low voltage side) and the positive side (high voltage side).
In a dot inversion driver, a reductions in chip size is needed by disposing low-voltage-dedicated circuits and high-voltage-dedicated circuits, respectively, by numbers each equal to not the total number of output terminals but xc2xd of the same, by taking advantage of the fact that a negative side (a to voltage side) and a positive side (a high voltage side) are alternately outputted from adjacent output terminals.
Since the construction of the low-voltage-dedicated circuits and the high-voltage-dedicated circuits (a decoder construction) aims at reducing chip size, it is necessary that the switching elements of grayscale voltage selection circuits, amplifier circuits and output selection circuits be formed of only NMOSs for the low-voltage-dedicated circuits as well as of only PMOSs for the high-voltage-dedicated circuits so that the number of elements can be reduced.
FIGS. 29 to 32 are circuit diagram illustrating specific examples of the constructions of a low-voltage-dedicated circuit and a high-voltage-dedicated circuit of a drain driver. FIGS. 29 and 30 show the low-voltage-dedicated circuit, while FIGS. 31 and 32 show the high-voltage-dedicated circuit. Incidentally, each pair of FIGS. 29 and 30 and FIGS. 31 and 32 show the corresponding circuit in the form of two divided sections, because both circuits have fine constructions. Circled numbers (1), (2), . . . denote lines which are respectively connected to each other between FIGS. 30 and 31 and between FIGS. 31 and 32. These circuits constitute an example of the construction of a drain driver capable of providing 64-level grayscale display.
In the low-voltage-dedicated circuit and the high-voltage-dedicated circuit shown in FIGS. 29 to 32, display data are inputted to input terminals D0P, D0N, D1P, D1N, . . . D5P and D5N and to input terminals D0PH, D0NH, D1PH, D1NH, . . . D5PH and D5NH, and 64 grayscale levels arc inputted to V00, V01, . . . V63 and to VH00, VH01, . . . VH63, respectively. Incidentally, a substrate bias BG of the circuit shown in FIGS. 29 and 30 is connected to ground (GND), while a substrate bias BG of the circuit shown in FIGS. 31 and 32 is connected to a power source (VLCD).
Negative-side (low-voltage-side) and positive-side (high-voltage-side) drain line driving voltages are outputted at output terminals YB and YA, respectively.
FIGS. 33 to 36 are circuit blocks illustrating other specific examples of the constructions of a low-voltage-dedicated circuit and a high-voltage-dedicated circuit of a drain driver. FIGS. 33 and 34 show the low-voltage-dedicated circuit, while FIGS. 35 and 36 show the high-voltage-dedicated circuit. Incidentally, similarly to each pair of FIGS. 29 and 30 and FIGS. 31 and 32, each pair of FIGS. 33 and 34 and FIGS. 35 and 36 show the corresponding circuit in the form of two divided sections, because both circuits have fine constructions. Circled numbers (1), (2), . . . denote lines which are respectively connected to each other between FIGS. 33 and 34 and between FIGS. 35 and 36. These circuits also constitute an example of the construction of a drain driver capable of providing 64-level grayscale display.
In the low-voltage-dedicated circuit and the high-voltage-dedicated circuit shown in FIGS. 33 to 36, display data are inputted to input terminals D1P, D0N, D0P, D1N, D3P, D2N, D2P, D3N, D5P, D4N, D4P and D5N and to input terminals D1PH, D0NH, D0PH, D1NH, D3PH, D2NH, D2PH, D3NH, D5PH, D4NH, D4PH and D5NH, and 64 grayscale voltages are inputted to V00, V01, . . . V63 and to VH00, VH01, . . . VH63, respectively.
Incidentally, a substrate bias BG of the circuit shown in FIGS. 33 and 34 is connected to ground (GND), while a substrate bias BG of the circuit shown in FIGS. 35 and 36 is connected to a power source (VLCD).
Negative-side (low-voltage-side) and positive-side (high-voltage-side) drain line driving voltages are outputted at output termminals YB and YA, respectively.
However, the maximum voltage selectable by the switching elements (NMOSs and PMOSs) which constitute the above-described drain driver depends on a threshold (Vth) determined by the substrate bias effect of a MOS which selects the highest grayscale level with respect to a substrate potential reference. For example, in the case of the NMOSs which constitute the circuit shown in FIGS. 29 and 30, letting VLCD stand for a voltage to be applied to a liquid crystal, i.e., the output voltage of the drain driver; Vmax the maximum selectable voltage; and (Vth0+xcex94Vth) the threshold voltage at the time of Vmax output, the following expression (1) is given:
VLCDxe2x88x92Vmax=Vth0+xcex94Vth.xe2x80x83xe2x80x83(1)
This leads to the problem that as the voltage VLCD is made lower, the maximum selectable voltage becomes smaller.
In the expression (1), VLCD represents the liquid crystal driving voltage, Vth0 represents Vth for a substrate bias of xe2x80x9c0xe2x80x9d, and xcex94Vth (V) represents an increase in Vth for a substrate bias of V.
In addition, if the output voltage of the drain driver is to be formed by the above-described asymmetric driving, there is the problem that the maximum selectable voltage becomes small on a side of polarity which widens its output voltage range, for example, on a negative side in an n-type of TFT.
Furthermore, although the output voltage range of the drain driver can be widened by forming the above-described switching elements as complementary MOSs (CMOSs), the chip area of the drain driver increases, and in a grayscale level selection circuit in particular, as the number of grayscale levels becomes larger, the influence of the increase in the chip area becomes larger and hinders the development of multilevel grayscale display. This increase in the chip area is a large obstacle to reductions in the frame sizes and the prices of liquid crystal display devices.
In addition, in an amplifier circuit and an output selection circuit of the low-voltage-dedicated circuit (low voltage decoder) and the high-voltage-dedicated circuit (high voltage decoder), it is necessary to widen their operating voltage ranges.
FIG. 37 is a circuit diagram illustrating a differential input portion which constitutes an amplifier circuit of a low-voltage-dedicated circuit of a related-art drain driver. A high-voltage-dedicated circuit also has a similar circuit. This differential input portion (chopper circuit) is made of only NMOSs which are respectively surrounded by circles in FIG. 37 (a differential input portion which constitutes an amplifier of a high-voltage-dedicated circuit is made of only PMOSs.)
FIG. 38 is a circuit diagram of an output selection circuit for selecting either one of the amplifier circuit output of the low-voltage-dedicated circuit or the amplifier circuit output of the high-voltage-dedicated circuit. This output selection circuit (output selector circuit) determines whether each of the amplifier circuit output, YH, of the high-voltage-dedicated circuit and the amplifier circuit output, YL, of the low-voltage-dedicated circuit should be outputted to YA or YB via a PMOS transistor (YH) or an NMOS transistor (YL) in accordance with selection signals (selector signals) ACKOP and ACKEN.
The maximum operating voltage in the circuit shown in FIGS. 37 and 38 depends on the threshold Vth determined by the substrate bias effect of each MOS switch. The maximum operating voltage Vmax is given by the following expression (2):
VLCDxe2x88x92Vmax greater than Vth0+xcex94Vth (Vmax).xe2x80x83xe2x80x83(2)
However, there is the problem that when Vmax=VLCD/2, an on-resistance (Ron) increases and a normal voltage cannot be outputted.
In a liquid crystal display device, gate drivers and an interface part are mounted on lateral sides of the screen of its liquid crystal panel, and drain drivers are mounted on the top or bottom side of the screen. In a dot inversion driving type of liquid crystal display device, each drain driver is provided with an output circuit for outputting a positive voltage and a negative voltage, and internal signals are switched therebetween by a polarity inverting signal, thereby effecting an output polarity inverting operation.
This output polarity inverting operation, switchover between input pixel data is effected in units of pixels (for example, 6 bits) (for example, D00-D05 (Y2n)←xe2x86x92D10-D15 (Y2n+1), and a switchover line is needed in a related-art circuit.
This leads to the problem that the switchover line for pixel data inputs across a reference voltage input terminal and a control signal input terminal from the pad arrangement of the chip of the drain driver cannot effectively utilize a layout space owing to a power source line, a center buffering circuit and the like, so that a desired chip size cannot be achieved.
FIG. 39 is a block diagram illustrating the construction of a drain driver, which includes first data latch circuits 401, control circuits 1, a buffer circuit, data switchover circuits 403, second data latch circuits 45, a voltage dividing circuit 6, level shifter circuits 9, a decoder circuit 7, an amplifier circuit (amplifying circuit) 8 and an amplifier output switchover circuit (amplifying circuit output switchover circuit) 11.
Normally, during an output polarity inverting operation, display data input signals are switched therebetween (in units of 2 pixelsxc3x976 bits) by polarity inverting signals, and amplifier output signals are switched therebetween in units of 2 outputs.
FIG. 40 is a circuit diagram of a related-art display data switchover circuit, which outputs the outputs of the display data input part 401 having first data latch circuits for latching input display data 1 and 2 to either of data lines 404 or 405 via a switchover line 402 and the switchover circuits 403.
This circuit adopts a CMOS type of multiplexer to which polarity inverting signals and a pair of display data inputs which determine an output-on state are inputted in units of 2 pixelsxc3x971 bit. This circuit is needed in the form of 6 pixelsxc3x976 bits.
FIG. 41 is a wiring diagram of the chip of the drain driver, and the input lines of the switchover circuit occupy an area of 2 pixelsxc3x976 bitsxc3x97(line width+line pitch).
In the switchover between display data inputs across the control signal input terminals and the reference voltage input terminals, the input lines of the switchover circuit needs to be arranged in such a manner as to avoid a power source line for the reference voltage input terminals and an internal control signal buffering circuit. This fact leads to the problem of increasing the area of the input lines of the switchover circuit to a further extent.
Moreover, to reduce a variation in a liquid crystal driving voltage output from an output amplifier circuit, as described previously, the polarity of an output voltage variation component is inverted and canceled in synchronism with a display frame period or the like by a chopper circuit, whereby an effective variation is reduced.
FIG. 42 is a block diagram illustrating the arrangement of a test terminal in a related-art drain driver. The chip of the drain driver is provided with amplifier circuits 423(1, 2, . . . (nxe2x88x921), n) which include built-in chopper circuits, respectively. Mounted on the chip are a chopper control signal generation circuit 421 for generating a control signal on the basis of, for example, a display frame period (frame start signal) of a liquid crystal panel, a level shifter circuit 422, the n number of amplifier circuits 423 which include built-in chopper circuits, respectively. A liquid crystal driving voltage output terminal 424 and a test terminal 425 are also formed on the chip.
It is important to make an inspection as to whether each of the chopper circuits for inverting the polarities of output voltage variation components normally operates. Since these variation components are minute, a chopper control signal to be supplied to the chopper circuits of the amplifier circuits is connected to the test terminal and a test is equivalently performed.
However, in the case of the related-art chip, since the test terminal 425 is arranged in the chip center portion, it is difficult to guarantee that the chopper control signal reaches an amplifier circuit located at a chip end.
In addition, since a frame start signal input terminal is arranged at only one location on the chip, in the case of a mounting package, such as a tape carrier package (TCP), which uses a one-layer metal interconnection or the like, the arrangement of pins on the package are limited by the arrangement of terminals on the chip, so that the frame start signal input terminal is allowed to be present at only one fixed location on the package.
In addition, in different liquid crystal display devices, there are some cases where different pin arrangements on TCPs are required for liquid crystal drivers having the same function, in terms of a problem such as the design of printed circuit boards. In this case, according to the related art, it is necessary to re-design chips having different pin arrangements, so that development costs and development periods become problems. In addition, there is the problem that the number of kinds of articles to be produced increase and a reduction in manufacturing cost due to a mass-production effect cannot be achieved.
Furthermore, in the related-art chip, the test terminal for the chopper control signals of the chopper circuits is arranged on only the side of the liquid crystal driving voltage output terminal connected to the liquid crystal panel, and a test of each of the chopper circuits is carried out with a probe inspection.
However, if such a chip is to be mounted on a liquid crystal panel in the state of being incorporated in a package such as a TCP, it is often impossible to lead out of the package the test terminal arranged on the side of the liquid crystal driving voltage output terminal of the chip, because limitations are imposed on the layout of lines of the liquid crystal driving voltage output terminal.
In case that a test terminal cannot be arranged on a package, there is the problem that it is impossible to detect a defective chopper control signal due to the assembly of the package.
The present invention is to solve the various problems of the above-described related art, and a first object of the present invention is to provide a liquid crystal display device in which the image quality of a liquid crystal panel can be made high by widening the liquid crystal driving voltage output range of each of a low-voltage-dedicated circuit and a high-voltage-dedicated circuit which are incorporated in a drain driver.
Another object of the present invention is to provide a liquid crystal display device in which a liquid crystal driving voltage VLCD is lowered by widening the liquid crystal driving voltage output range of a drain driver, whereby the overall power consumption can be reduced.
Another object of the present invention is, to provide a liquid crystal display device in which the liquid crystal driving voltage output range of a drain driver is widened with an increase in chip area being restrained, whereby its frame size and price can be reduced.
Another object of the present invention is to provide a liquid crystal display device in which an inspection can easily be made as to whether the chopper control signal of a drain driver reaches an amplifier circuit located at a chip end, and it is possible to easily guarantee that the chopper control signal reaches the amplifier circuit, whereby a variation in liquid crystal driving voltage output is reduced to improve display quality.
Another object of the present invention is to provide a liquid crystal display device in which one chip can deal with different packages having different pin positions for frame start signals of drain drivers whereby a development cost for chip and an increase in the number of type to be produced can be reduced.
Another object of the present invention is to provide a liquid crystal display device in which it is possible to comprehensively guarantee a frame start signal input and the operation of a chopper signal generation circuit even after the packaging of a drain driver.
Representative constructions of the present invention for achieving the above-described objects will be described below in brief.
(1) A liquid crystal display device is comprising: a liquid crystal panel having a plurality of scanning signal lines and a plurality of video signal lines and a liquid crystal panel having a plurality of pixels to which video signal voltages corresponding to A number of pieces of display data are to be applied via the video signal lines by a plurality of video signals; and-video signal line driving means for supplying to the video signal lines the video signal voltages corresponding to the A number of pieces of display data,
the video signal line driving means having: a power source circuit for outputting K number of grayscale reference voltages; a plurality of grayscale generation circuits for generating grayscale voltages corresponding to the A number of pieces of display data, for the respective video signal lines; and a video signal line driving circuit made of a plurality of amplifier circuits and output selecting circuits for amplifying the grayscale voltages and outputting video signal voltages corresponding to the display data to the respective video signal lines,
the video signal lines driving means including: grayscale voltage generation means for dividing the K number of grayscale reference voltages outputted from the power source circuit to generate M-level grayscale voltages and selecting one of the generated grayscale voltages; and output means for making maximum output levels for N grayscale levels out of the M grayscale levels greater than maximum output levels for the other (M-N) grayscale levels,
the grayscale voltage generation means being a grayscale voltage selection circuit having switching elements corresponding to the A number of pieces of display data; among switching elements for selecting display data for the N grayscale levels, switching elements corresponding to the B number of pieces of display data among the A number of pieces of display data having the switching characteristics of being turned on or off at all the N grayscale levels, and on-resistances of switching elements corresponding to (A-B) number of pieces of display data being smaller than on-resistances of switching elements for selecting display data for the (M-N) grayscale levels.
(2) The liquid crystal display device described in the above paragraph (1) is characterized in that the switching elements corresponding to the B number of pieces of display data are CMOS transistors.
(3) The liquid crystal display device described in the above paragraph (1) or (2) is characterized in that threshold voltages of the switching elements corresponding to the (A-B) number of pieces of display data are smaller than threshold voltages of the switching elements for selecting display data for the (M-N) grayscale levels.
(4) The liquid crystal display device described in the above paragraph (1) is characterized in that each of the amplifier circuits includes a switching clement for effecting switchover between an input part and an output part, the switching element for effecting switchover between the input part and the output part being a switching element capable of outputting an output level not lower than the maximum output levels for the N grayscale levels.
(5) The liquid crystal display device described in the above paragraph (4) is characterized in that the switching element for effecting switchover between the input part and the output part is a CMOS transistor.
(6) The liquid crystal display device described in the above paragraph (4) is characterized in that each of the output selection circuits includes a switching element capable of outputting an output level not lower than the maximum output levels for the N grayscale levels.
(7) The liquid crystal display device described in the above paragraph (6) is characterized in that each of the output selection circuits is a CMOS transistor.
(8) The liquid crystal display device described in the above paragraph (1) is characterized in that the video signal line driving means outputs a positive video signal driving voltage and a negative video signal driving voltage at the time of each output, and two switchover circuits capable of generating positive, negative and output-off states of two different pieces of display data are used, the outputs of these two switchover circuits being connected to one data line in a switched manner.
(9) The liquid crystal display device described in the above paragraph (8) is characterized in that the circuit construction of (8) is used and another control input terminal and a reference voltage input terminal are arranged between display data input terminals which are laterally uniformly arranged on a chip.
(10) The liquid crystal display device described in the above paragraph (1) is characterized in that an inspection terminal for an internal control signal to be supplied to the amplifier circuits is arranged at an end of a control signal line.
(11) The liquid crystal display device described in the above paragraph (10) is characterized in that the internal control signal is connected to the inspection terminal through an output circuit for improving the capability to drive an external load.
(12) The liquid crystal display device described in the above paragraph (10) is characterized in that the output from a circuit for generating the internal control signal is connected to an arbitrary position on a signal line which propagates the internal control signal, and the inspection terminal is arranged at each of a plurality of ends of the internal control signal line.
(13) The liquid crystal display device described in the above paragraph (10) is characterized in that the output from a circuit for generating the internal control signal is connected to one end of a signal line which propagates the internal control signal, and the inspection terminal is arranged at the other end of the signal line.
(14) The liquid crystal display device described in the above paragraphs (9) to (13) is characterized in that frame start signal input terminals are arranged at a plurality of positions on the chip.
(15) The liquid crystal display device described in the above paragraphs (9) to (14) is characterized in that an input terminal for the internal control signal is arranged on an input terminal side in addition to a liquid crystal driving output terminal side.
According to the above-described constructions, it is possible to obtain a liquid crystal display device which enables higher image quality, lower power consumption, suppression of an increase in chip area, a smaller frame size and a lower price.
The present invention is not limited to any of the above-described constructions, and also encompasses constructions which will be disclosed in the following description of embodiments of the invention. In addition, various modifications of the present invention can be made without departing from the technical concepts disclosed in the above-described constructions and the embodiments of the invention.